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HM628128DI Series
1 M SRAM (128-kword x 8-bit)
ADE-203-999A (Z) Preliminary Rev. 0.1 Jul. 8, 1999 Description
The Hitachi HM628128DI Series is 1-Mbit static RAM organized 131,072-kword x 8-bit. HM628128DI Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS process technology. The HM628128DI Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP, standard 32-pin plastic SOP.
Features
* Single 5 V supply: 5 V 10% * Access time: 70 ns (max) * Power dissipation Active: 30 mW/MHz (typ) Standby: 10 W (typ) * Completely static memory. No clock or timing strobe required * Equal access and cycle times * Common data input and output Three state output * Directly TTL compatible all inputs * Battery backup operation 2 chip selection for battery backup * Temperature range: -40 to +85C
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specification.
HM628128DI Series
Ordering Information
Type No. HM628128DLPI-7 HM628128DLFPI-7 Access time 70 ns 70 ns Package 600-mil 32-pin plastic DIP (DP-32) 525-mil 32-pin plastic SOP (FP-32D)
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HM628128DI Series
Pin Arrangement
32-pin DIP/SOP
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3
Pin Description
Pin name A0 to A16 I/O0 to I/O7 CS1 CS2 WE OE VCC VSS NC Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Power supply Ground No connection
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HM628128DI Series
Block Diagram
LSB A12 A7 A6 A5 A4 A3 A2 A1 A0 A10 MSB Row decoder
* * * * *
VCC VSS
Memory matrix 512 x 2,048
I/O0 Input data control I/O7
* *
Column I/O Column decoder
* *
LSB
A14 A16 A15 A13 A8 A9 A11
* *
MSB
CS1 CS2 WE OE
Timing pulse generator Read/Write control
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HM628128DI Series
Operation Table
CS1 H x L L L L CS2 x L H H H H WE x x H L L H OE x x L H L H I/O High-Z High-Z Dout Din Din High-Z Operation Standby Standby Read Write Write Output disable
Note: H: V IH, L: VIL, x: VIH or VIL
Absolute Maximum Ratings
Parameter Power supply voltage relative to V SS Terminal voltage on any pin relative to V SS Power dissipation Storage temperature range Storage temperature range under bias Symbol VCC VT PT Tstg Tbias Value -0.5 to +7.0 -0.5* to V CC + 0.3* 1.0 -55 to +125 -40 to +85
1 2
Unit V V W C C
Notes: 1. VT min: -1.5 V for pulse half-width 30 ns 2. Maximum voltage is +7.0 V
DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Note: VIH VIL Ta Min 4.5 0 2.4 -0.3 -40 Typ 5.0 0 -- -- -- Max 5.5 0 VCC + 0.3 0.6 85 Unit V V V V C 1 Note
1. VIL min: -1.5 V for pulse half-width 30 ns
5
HM628128DI Series
DC Characteristics
Parameter Input leakage current Output leakage current Symbol |ILI| |ILO | Min -- -- Typ*1 -- -- Max 1 1 Unit A A Test conditions Vin = VSS to V CC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, V I/O = VSS to V CC CS1 = VIL, CS2 = VIH, others = VIH/V IL, I I/O = 0 mA Min cycle, duty = 100% I I/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/V IL Cycle time = 1 s, duty = 100%, I I/O = 0 mA, CS1 0.2 V, CS2 V CC - 0.2 V, VIH V CC - 0.2 V, VIL 0.2 V (1) CS1 = VIH, CS2 = VIH, or (2) CS2 = VIL 0 V Vin (1) 0 V CS2 0.2 V or (2) CS1 V CC - 0.2 V, CS2 V CC - 0.2 V I OH = -1 mA I OL = 2.1 mA
Operating current Average operating current
I CC I CC1
-- --
-- --
15 60
mA mA
I CC2
--
6
20
mA
Standby current
I SB I SB1*2
-- --
-- 2
2 100
mA A
Output high voltage Output low voltage
VOH VOL
2.4 --
-- --
-- 0.4
V V
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and specified loading, and not guaranteed. 2. This characteristics is guaranteed only for L-version.
Capacitance (Ta = +25C, f = 1 MHz)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Typ -- -- Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1
1. This parameter is sampled and not 100% tested.
6
HM628128DI Series
AC Characteristics (Ta = -40 to +85C, VCC = 5.0 V 10%, unless otherwise noted.)
Test Conditions * * * * * Input pulse levels: VIL = 0.6 V, VIH = 2.4 V Input rise and fall time: 5 ns Input timing reference levels: 1.5 V Output timing reference level: 1.5 V Output load:1 TTL Gate+ CL (100 pF) (Including scope and jig)
Read Cycle
HM628128DI -7 Parameter Read cycle time Address access time Chip select access time Symbol t RC t AA t ACS1 t ACS2 Output enable to output valid Output hold from address change Chip selection to output in low-Z t OE t OH t CLZ1 t CLZ2 Output enable to output in low-Z Chip deselection to output in high-Z t OLZ t CHZ1 t CHZ2 Output disable to output in high-Z t OHZ Min 70 -- -- -- -- 10 10 10 5 0 0 0 Max -- 70 70 70 35 -- -- -- -- 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes
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HM628128DI Series
Write Cycle
HM628128DI -7 Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from output in high-Z Output disable to output in high-Z WE to output in high-Z Symbol t WC t AW t CW t WP t AS t WR t DW t DH t OW t OHZ t WHZ Min 70 60 60 50 0 0 30 0 5 0 0 Max -- -- -- -- -- -- -- -- -- 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 8 1, 2, 8 5 4, 13 6 7 Notes
Notes: 1. t CHZ, tOHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap (tWP) of a low CS1, a high CS2, and a low WE. A write begins at the latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low, and WE going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from CS1 going low or CS2 going high to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earlier of WE or CS1 going high or CS2 going low to the end of write cycle. 8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 9. If the CS1 goes low or CS2 going high simultaneously with WE going low or after WE going low, the output remain in a high impedance state. 10. Dout is the same phase of the write data of this write cycle. 11. Dout is the read data of next address. 12. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 13. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. t WP tDW min + tWHZ max
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HM628128DI Series
Timing Waveforms
Read Cycle (WE = VIH)
tRC Address Valid address tAA CS1 tACS1 tCLZ1 CS2 tACS2 tCLZ2 tCHZ2 tCHZ1
OE tOE tOLZ Dout High impedance tOHZ tOH Valid data
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HM628128DI Series
Write Cycle (1) (OE Clock)
tWC Address Valid address tAW OE tCW CS1
*9
tWR
CS2 tAS WE tOHZ High impedance Dout tDW Din tDH tWP
Valid data
10
HM628128DI Series
Write Cycle (2) (OE = VIL )
tWC Address Valid address tCW CS1
*9
tWR
CS2
tAW tWP WE tAS tWHZ tOW
*10 *11
tOH
Dout
High impedance tDW tDH
*12
Din
Valid data
11
HM628128DI Series
Low VCC Data Retention Characteristics (Ta = -40 to +85C)
Parameter VCC for data retention Symbol VDR Min 2.0 Typ* 3 -- Max -- Unit V Test conditions*2 Vin 0V (1) 0 V CS2 0.2 V or (2) CS2 V CC - 0.2 V CS1 V CC - 0.2 V VCC = 3.0 V, Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 V CC - 0.2 V, CS1 V CC - 0.2 V See retention waveform
Data retention current
I CCDR*1
--
1.0
50
A
Chip deselect to data retention time Operation recovery time
t CDR tR
0 t RC*
4
-- --
-- --
ns ns
Notes: 1. This characteristic is guaranteed only for L-version, 30 A max. at Ta = -40 to +40C. 2. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 VCC - 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 3. Typical values are at VCC = 3.0 V, Ta = +25C and specified loading, and not guaranteed. 4. t RC = read cycle time.
Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)
tCDR VCC 4.5 V Data retention mode tR
2.4 V VDR CS1 0V CS1 VCC - 0.2 V
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HM628128DI Series
Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)
tCDR VCC 4.5 V CS2 VDR 0.6 V 0V 0 V CS2 0.2 V Data retention mode tR
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HM628128DI Series
Package Dimensions
HM628128DLPI Series (DP-32)
Unit: mm
32
41.90 42.50 Max
17 13.4 13.7 Max
1 2.30 Max
5.08 Max
1.20
16 15.24
0.51 Min 2.54 Min
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
Hitachi Code JEDEC EIAJ Weight (reference value)
DP-32 -- Conforms 5.1 g
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HM628128DI Series
HM628128DLFPI Series (FP-32D)
Unit: mm
20.45 20.95 Max 32 17
1 1.00 Max
16 3.00 Max *0.22 0.05 0.20 0.04
11.30
14.14 0.30 1.42
0.12 0.15 + 0.10 -
0 - 8 0.80 0.20
1.27 *0.40 0.08 0.38 0.06
0.10 0.15 M
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
FP-32D Conforms -- 1.3 g
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HM628128DI Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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